1. Field of the Invention
The present invention relates to a method of forming thin film transistors (xe2x80x9cTFTxe2x80x9ds) for use in a liquid crystal display (LCD) and, more particularly, to a method with four mask steps for forming TFTs for use in an LCD.
2. Description of the Related Art
Currently, liquid crystal display (LCD), having the advantages of low power consumption, thin type, light weight and low driving-voltage, is commonly used. The applied electric field on the LCD changes the alignment of liquid crystals that possess the characteristics of dielectric anisotropy and conducting anisotropy, and the accompanied optical effects are transformed into visual variation. An LCD employing a thin film transistor (TFT) as an active device is referred to as a TFT-LCD, wherein the TFT provides low power consumption, a thin profile, light weight and low driving-voltage. However, since the TFT is thinner than traditional transistors, TFT manufacture consists of multiple photolithography steps using more than seven masks and thereby creates problems of poor yield and high costs. Seeking to improve the above-mentioned problems, various TFT structures and corresponding methods of making them have been developed to reduce the required cycles of photolithography.
FIG. 1 is a top view of a conventional TFT-LCD. FIGS. 2A to 2F are cross-sectional diagrams along line IIxe2x80x94II showing a conventional method of forming a TFT-LCD according to the prior art. As shown in FIG. 1, the conventional TFT-LCD has a plurality of gate lines 2 extending transversely and arranged in parallel, and a plurality of data lines 4 extending lengthwise and arranged in parallel, wherein approximately rectangular areas arranged in matrix formed by adjacent gate lines 2 and data lines 4 serve as pixel areas 6. Each of the pixel areas 6 has a pixel electrode 8 covering the approximately rectangular area, and a TFT structure 10 disposed near the intersection of the gate line 2 and the data line 4. The TFT structure 10 has a gate electrode 12 lengthwise projecting from the gate line 2, a drain electrode 14 electrically connected to the pixel electrode 8, and a source electrode 6 transversely projecting from the data line 4.
In the conventional method, an etch-stop process is employed to form the TFT structure 10. As shown in FIG. 2A, using photolithography and etching with a first mask, a first metal layer deposited on a glass substrate 18 is patterned to form the gate line 2. A lengthwise projecting portion of the gate line 12 serves as the gate electrode 12 of the TFT structure 10. As shown in FIG. 2B, a gate insulating layer 20 of silicon nitride and silicon oxide, a first semiconductor layer 22 of amorphous silicon (a-Si), and an etch-stop layer 24 of silicon nitride are successively formed on the glass substrate 18. Then, using photolithography and etching from the back of the glass substrate 18 with a second mask, the etch-stop layer 24 over the gate electrode 12 remains.
Referring to FIG. 2C, a second semiconductor layer 26 of n+-doped a-Si and a second metal layer are successively formed on the glass substrate 18. Next, using photolithography and etching with a third mask, the second metal layer is patterned to form the data line 4, wherein a transversely projecting portion of the data line 4 covers a part of the lengthwise projecting portion of the gate line 2. Also, the patterned second metal layer over the gate electrode 12 is separated by a first opening 30 to serve as the source electrode 16 and the drain electrode 14 respectively. Thereafter, as shown in FIG. 2D, using the patterned second metal layer as a mask, the second semiconductor layer 26 and the first semiconductor layer 22 are continuously removed until the gate insulating layer 20 is exposed. Meanwhile, using the etch-stop layer 24 as the etching end-point, the second semiconductor layer 26 at the bottom of the first opening 30 is removed. Thereby, the second semiconductor layer 26 is divided into a drain region 261 and a source region 262.
Referring to FIG. 2E, a protection layer 32 is conformally formed on the exposed surface of the glass substrate 18 and fills the first opening 30. Then, using photolithography and etching with a fourth mask, a second opening 34 is formed to expose a predetermined region of the top of the drain electrode 14. Finally, as shown in FIG. 2F, a conductive layer 36 is conformally deposited on the protection layer 32 and fills the second opening 34, and then the conductive layer 36 is patterned as the pixel electrode 8 using photolithography and etching with a fifth mask. The conductive layer 36 is of metallic materials. Alternatively, the conductive layer 36 is indium tin oxide (ITO) for increasing the aperture ratio of the TFT-LCD.
The etch-stop layer 24 is mainly used to protect the first semiconductor layer 22 from over-etching during the formation of the drain region 261 and the source region 262. However, since the second mask is needed to pattern the etch-stop layer 24, the five mask steps cannot be further reduced in the conventional method. Therefore, the problem of exposure error, increasing process complexity and prolonging exposure time, becomes worse when performing five cycles of photolithography. This causes low throughput, high production costs, and imperfections in devices. Thus, a method of forming the TFT structure with reduced mask steps solving the aforementioned problems is called for.
The present invention provides an etch-stop process to form a TFT structure with four mask steps for solving the problems caused by performing many cycles of photolithography.
The method of forming a TFT structure is performed on a glass substrate. First, a first metal layer deposited on the glass substrate is patterned with a first mask to form a gate line and a gate electrode. Next, a gate insulating layer, a first semiconductor layer and an etch-stop layer are successively formed, and then a backside exposure patterns the etch-stop layer. Thus, the remaining part of the etch-stop layer is disposed over the gate electrode and the gate line. Next, a second semiconductor layer and a second metal layer are successively formed, and then the second metal layer is patterned with a second mask to form a data line perpendicular to the gate line. Thereafter, the second semiconductor layer and the first semiconductor layer not covered by the second metal layer are removed. Next, a first protection layer formed on the exposed surface of the glass substrate is patterned with a third mask to form a first opening and a second opening, wherein the first opening is over the gate electrode and the second opening is over a predetermined drain electrode. Next, a conductive layer and a photoresist layer successively formed on the exposed surface of the glass substrate are patterned with a fourth mask to form a pattern of a predetermined pixel electrode. Finally, after removing the second metal layer and the second semiconductor layer underlying the first opening to expose the etch-stop layer, a second protection layer is formed on the first protection layer to fill the first opening.
Accordingly, it is a principal object of the invention to provide a method with reduced mask steps.
It is another object of the invention to employ backside exposure with the gate line and the gate electrode mask self-aligning the etch-stop pattern.
Yet another object of the invention is to alleviate the problem of exposure error.
It is a further object of the invention to increase throughput, decrease production costs, and improve properties of devices.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.